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rev 1.3 k7p321888m 1mx36 & 2mx18 sram K7P323688M dec. 2005 - 1 - 32mb m-die lw sram specification 119bga with pb & pb-free (rohs compliant) * samsung electronics reserves the right to change products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sams ung products, contact your nearest samsung office. 2. samsung products are not intended for use in life suppor t, critical care, medical, safety equipment, or simi- lar applications where product failure could result in lo ss of life or personal or ph ysical harm, or any military or defense application, or any governmental procuremen t to which special terms or provisions may apply.
rev 1.3 k7p321888m 1mx36 & 2mx18 sram K7P323688M dec. 2005 - 2 - 1mx36 & 2mx18 synchronous pipelined sram the attached data sheets are prepared and approved by samsung electronics. samsung electr onics co., ltd. reserve the right to change the specifications. samsun g electronics will evaluate and reply to y our requests and questions on the parameter s of this device. if you have any questions, please contact the sams ung branch office near your office, call or cortact headquar ters. revision history rev. no. rev. 0.0 rev. 0.1 rev. 0.2 rev. 0.3 rev. 0.4 rev. 1.0 rev. 1.1 rev. 1.2 rev. 1.3 remark advance advance advance advance advance final final final final history - initial document - recommended dc operating conditions are changed max v dif-clk : v ddq +0.3 -> v ddq +0.6 - ac characteristics are changed t avkh / t dvkh / t wvkh / t svkh : 0.4 / 0.4 / 0.4 - > 0.3 / 0.3 / 0.3 t khax / t khdx / t khwx / t khsx : 0.5 / 0.6 / 0.7 - > 0.5 / 0.5 / 0.5 t khax / t khdx / t khwx / t khsx : 1.6 / 1.7 / 2.0 - > 1.5 / 1.6 / 2.0 - package pin configuration are changed numbering each sa pins. - ac characteristics are changed t khqv (-33) : 0.5 - > 0.6 - pin capacitance is changed add clock pin capacitance - fill the themal data - remove 333mhz bin - jtag dc operating conditions are changed change vih, vil voh, vol - add pb free. - modify package dimensions draft date apr. 2002 feb. 2003 feb. 2003 mar. 2003 may 2003 sep. 2004 oct. 2004 oct. 2005 dec. 2005 document title
rev 1.3 k7p321888m 1mx36 & 2mx18 sram K7P323688M dec. 2005 - 3 - 1mx36 & 2mx18 synchr onous pipelined sram features org. part number maximum frequency access time 1mx36 K7P323688M-h(g)c30 300mhz 1.7 K7P323688M-h(g)c25 250mhz 2.0 2mx18 k7p321888m-h(g)c30 300mhz 1.7 k7p321888m-h(g)c25 250mhz 2.0 ? 1mx36 or 2mx18 organizations. ? 1.8v v dd /1.5v or 1.8v v ddq . ? hstl input and output levels. ? differential, hstl clock inputs k, k . ? synchronous read and write operation ? registered input and registered output ? internal pipeline latches to support late write. ? byte write capability(four byte write selects, one for each 9bits) ? synchronous or asynchronous output enable. ? power down mode via zz signal. ? programmable impedance output drivers. ? jtag boundary scan (subset of ieee std. 1149.1). ? 119(7x17) flip chip ball grid array package(14mmx22mm). pin description pin name pin description pin name pin description k, k differential clocks zz asynchronous power down san synchronous address input zq output driver impedance control dqn bi-directional data bus tck jtag test clock ss synchronous select tms jtag test mode select sw synchronous global write enable tdi jtag test data input sw a synchronous byte a write enable tdo jtag test data output sw b synchronous byte b write enable v ref hstl input reference voltage sw c synchronous byte c write enable v dd power supply sw d synchronous byte d write enable v ddq output power supply m 1 , m 2 read protocol mode pins (m 1 =v ss , m 2 =v ddq ) v ss gnd g asynchronous output enable nc no connection functional block diagram 20 or 21 k,k ss g memory array 1mx36 data out data in s/a array mux0 w/d array 36 or 18 36 or 18 36 or 18 36 or 18 2:1 mux dec. sa[0:19] address register read sw zz internal clock generator write address register data out register clock buffer control register dq 36 or 18 36 or 18 36 or 18 36 or 18 xdin data in register (2 stage) 20 or 21 control logic e way oe 36 or 18 or [0:20] 2mx18 * g : lead free package
rev 1.3 k7p321888m 1mx36 & 2mx18 sram K7P323688M dec. 2005 - 4 - package pin configurations (top view) K7P323688Mk7p321888m(1mx36) 1 2 3 4 5 6 7 a v ddq sa 13 sa 10 nc sa 7 sa 4 v ddq b nc sa 18 sa 9 sa 19 sa 8 sa 17 nc c nc sa 12 sa 11 v dd sa 6 sa 5 nc d dqc 8 dqc 9 v ss zq v ss dqb 9 dqb 8 e dqc 6 dqc 7 v ss ss v ss dqb 7 dqb 6 f v ddq dqc 5 v ss g v ss dqb 5 v ddq g dqc 3 dqc 4 sw cncsw bdqb 4 dqb 3 h dqc 1 dqc 2 v ss nc v ss dqb 2 dqb 1 j v ddq v dd v ref v dd v ref v dd v ddq k dqd 1 dqd 2 v ss kv ss dqa 2 dqa 1 l dqd 3 dqd 4 sw dk sw adqa 4 dqa 3 m v ddq dqd 5 v ss sw v ss dqa 5 v ddq n dqd 6 dqd 7 v ss sa 0 v ss dqa 7 dqa 6 p dqd 8 dqd 9 v ss sa 1 v ss dqa 9 dqa 8 r nc sa 15 m 1 v dd m 2 sa 2 nc t nc nc sa 14 sa 16 sa 3 nc zz u v ddq tms tdi tck tdo nc v ddq k7p321888m(2mx18) 1 2 3 4 5 6 7 a v ddq sa 13 sa 10 nc sa 7 sa 4 v ddq b nc sa 19 sa 9 sa 20 sa 8 sa 17 nc c nc sa 12 sa 11 v dd sa 6 sa 5 nc d dqb 1 nc v ss zq v ss dqa 9 nc e nc dqb 2 v ss ss v ss nc dqa 8 f v ddq nc v ss g v ss dqa 7 v ddq g nc dqb 3 sw bnc nc ncdqa 6 h dqb 4 nc v ss nc v ss dqa 5 nc j v ddq v dd v ref v dd v ref v dd v ddq k nc dqb 5 v ss kv ss nc dqa 4 l dqb 6 nc nc k sw adqa 3 nc m v ddq dqb 7 v ss sw v ss nc v ddq n dqb 8 nc v ss sa 0 v ss dqa 2 nc p nc dqb 9 v ss sa 1 v ss nc dqa 1 r nc sa 15 m 1 v dd m 2 sa 2 nc t nc sa 18 sa 14 nc sa 3 sa 16 zz u v ddq tms tdi tck tdo nc v ddq
rev 1.3 k7p321888m 1mx36 & 2mx18 sram K7P323688M dec. 2005 - 5 - function description the K7P323688M and k7p321888m are 37,748,736 bit synchronous pipeline mode sram. it is organized as 1,048,576 words of 36 bits(or 2,097,152 words of 18 bits)and is implemented in samsung s advanced cmos technology. single differential hstl level k clocks are used to initiate read/write operation and all internal operations are self-timed. a t the rising edge of k clock, all addresses, write enabl es, synchronous select and data ins are registered internally. data outs are updated from output registers at the next rising edge of k clock. an inte rnal write data buffer allows write data to follow one cycle a fter addresses and controls. the package is 119(7x17) ball grid array with balls on a 1.27mm pitch. mode control there are two mode control select pins (m 1 and m 2 ) used to set the proper read protocol. th is sram supports single clock pipelined operating mode. for proper specified device operation, m 1 must be connected to v ss and m 2 must be connected to v ddq . these mode pins must be set at power-up and must not change during device operation. power-up/power-down supply voltage sequencing the following power-up supply vo ltage application is recommended: v ss , v dd , v ddq , v ref , then v in . v dd and v ddq can be applied simultaneously, as long as v ddq does not exceed v dd by more than 0.5v during power-up. the following power-down supply voltage removal sequence is recommended: v in , v ref , v ddq , v dd , v ss . v dd and v ddq can be removed simultaneously, as long as v ddq does not exceed v dd by more than 0.5v during power-down. sleep mode sleep mode is a low power mode initiated by bringing the asynch ronous zz pin high. during sleep mode, all other inputs are igno red and outputs are brought to a high-impedance state. sleep mode current and output high-z are guaranteed after the specified slee p mode enable time. during sleep mode the memory array data content is preserved. sleep mode must not be initiated until after al l pending operations have completed, sinc e any pending operation will not guaranteed once sleep mode is initiated. normal opera- tions can be resumed by bringing the zz pin low, but only after the specified sleep mode recovery time. bypass read operation bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are identical. for this case, data outputs are from the data in regi sters instead of sram array. bypass read operation occurs on a byte to byte basis. if only one byte is written during a write operation but a read operation is required on the same address, a partia l bypass read operation occurs since the new byte data is from the data in registers while the remai ng bytes are from sram arry. write operation(late write) during write operations, addresses and cont rols are registered at the first rising edge of k clock and data inputs are register ed at the following rising edge of k clock. write addresses and data i nputs are stored in the data in registers until the next write oper ation, and only at the next write opeation are data inputs fully written in to sram array. byte write operation is supported using sw[ a:d] and the timing of sw[ a:d] is the same as the sw signal. programmable impedance output driver the data output driver impedance is adjusted by an ex ternal resistor, rq, connected between zq pin and v ss , and is equal to rq/5. for example, 250 ? resistor will give an output impedance of 50 ? . output driver impedance tolerance is 15% by test(10% by design) and is periodically readjusted to reflec t the changes in supply voltage and temperatur e. impedance updates occur early in cycle s that do not activate the outputs, such as deselect cycles. they may also occur in cycles initiated with g high. in all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the sram. imped- ance updates occur no more often than every 32 clock cycles. cl ock cycles are counted whether the sram is selected or not and proceed regardless of the type of cycle being executed. therefore, the user can be assu red that after 33 continuous read cycles have occurred, an impedance update will occur the next time g are high at a rising edge of the k clock. there are no power up requirements for the sram. however, to guarantee optimum output driver impedance after power up, the sram needs 1024 non- read cycles. the output buffers can also be programmed in a minimum impedance configurat ion by connecting zq to v ss or v ddq . read operation during read operations, addresses and controls are registered du ring the first rising edge of k cl ock and then the internal arr ay is read between first rising and falling edges of k clock. data outputs are updated from output registers off the falling edge of k clock. during consecutive read operations where the address is the same, the data output must be held constant without any glitches. t his characteristic is because the sr am will be read by devices that will operate sl ower than the sram frequency and will require mu lti- ple sram cycles to perform a single read operation.
rev 1.3 k7p321888m 1mx36 & 2mx18 sram K7P323688M dec. 2005 - 6 - truth table note : k & k are complementary k zz g ss sw sw a sw b sw c sw d dqa dqb dqc dqd operation xhxxxxxxxhi-zhi-zhi-zhi-zpower down m ode. no operation xlhxxxxxxhi-zhi-zhi-zhi-zoutput disabled. l lhxxxxxhi-zhi-zhi-zhi-zoutput disabled. no operation l l lhxxxxd out d out d out d out read cycle l x l l h h h h hi-z hi-z hi-z hi-z no bytes written lxlllhhhd in hi-z hi-z hi-z write first byte lxllhlhhhi-zd in hi-z hi-z write second byte l x l l h h l h hi-z hi-z d in hi-z write third byte l x l l h h h l hi-z hi-z hi-z d in write fourth byte lxlllllld in d in d in d in write all bytes recommended dc operating conditions note :1. these are dc test criteria. dc design criteria is v ref 50mv. the ac v ih /v il levels are defined separately for measuring timing parameters. 2. v ih (max)dc= v ddq +0.3, v ih (max)ac= 2.6 v (2.1v for dqs) (pulse width 20% of cycle time). 3. v il (min)dc= - 0.3v, v il (min)ac=-1.0v (-0.5v for dqs) (pulse width 20% of cycle time). parameter symbol min typ max unit note core power supply voltage v dd 1.7 1.8 1.9 v output power supply voltage v ddq 1.4 1.8 1.9 v input high level v ih v ref +0.1 - v ddq +0.3 v 1, 2 input low level v il -0.3 - v ref -0.1 v1, 3 input reference voltage v ref 0.7 0.9 0.95 v clock input signal voltage v in -clk -0.3 - v ddq +0.3 v clock input differential voltage v dif -clk 0.1 - v ddq +0.6 v clock input common mode voltage v cm -clk 0.7 0.9 0.95 v absolute maximum ratings note : power dissipation capability will be dependent upon package characteristics and use envi ronment. see enclosed thermal impeda nce data. stresses greater than those listed under " absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other c onditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condit ions for extended periods may affect reliability. parameter symbol value unit core supply voltage relative to v ss v dd -0.5 to 2.3 v output supply voltage relative to v ss v ddq -0.5 to 2.3 v voltage on any pin relative to v ss v in -0.5 to v ddq +0.5 (2.3v max )v output short-circuit current(per i/o) i out 25 ma operating temperature t opr 0 to 70 c storage temperature t str -55 to 125 c
rev 1.3 k7p321888m 1mx36 & 2mx18 sram K7P323688M dec. 2005 - 7 - dc characteristics note :1. minimum cycle. i out =0ma. 2. 50% read cycles. 3. |i oh |=(v ddq /2)/(rq/5) 15% @v oh =v ddq /2 for 175 ? rq 350 ? . 4. |i ol |=(v ddq /2)/(rq/5) 15% @v ol =v ddq /2 for 175 ? rq 350 ? . 5. programmable impedance output buffer mode. the zq pin is connected to v ss through rq. 6. minimum impedance output buffer mode. the zq pin is connected to v ss or v ddq . parameter symbol min max unit note average power supply operating current-x36 (v in =v ih or v il , zz & ss =v il ) i dd30 i dd25 - 620 550 ma 1, 2 average power supply operating current-x18 (v in =v ih or v il , zz & ss =v il ) i dd30 i dd25 - 570 500 ma 1, 2 power supply standby current (v in =v ih or v il , zz=v ih ) i sbzz -70ma1 active standby power supply current (v in =v ih or v il , ss =v ih , zz=v il ) i sbss - 200 ma 1 input leakage current (v in =v ss or v ddq ) i li -1 1 a output leakage current (v out =v ss or v ddq , dq in high-z) i lo -1 1 a output high voltage(programmable impedance mode) v oh1 v ddq /2 v ddq v3,5 output low voltage(programmable impedance mode) v ol1 v ss v ddq /2 v 4,5 output high voltage(i oh =-0.1ma) v oh2 v ddq -0.2 v ddq v6 output low voltage(i ol =0.1ma) v ol2 v ss 0.2 v 6 output high voltage(i oh =-6ma) v oh3 v ddq -0.4 v ddq v6 output low voltage(i ol =6ma) v ol3 v ss 0.4 v 6 pin capacitance note : periodically sampled and not 100% tested.(t a =25 c, f=1mhz) parameter symbol test condition min max unit input capacitance c in v in =0v - 4 pf data output capacitance c out v out =0v - 5 pf clock capacitance c clk v clk =0v - 5 pf
rev 1.3 k7p321888m 1mx36 & 2mx18 sram K7P323688M dec. 2005 - 8 - ac test conditions (t a =0 to 70 c, rq= 250 ? ) note : 1. v ddq should never be higher than v dd. parameter symbol value unit note core power supply voltage v dd 1.7~1.9 v output power supply voltage v ddq 1.8 v 1 input high/low level v ih /v il v ddq /2 0.5 v 1 input reference level v ref v ddq /2 v 1 input rise/fall time t r /t f 0.5/0.5 ns input and out timing reference level v ddq /2 v 1 clock input timing reference level cross point v 50 ? 50 ? ac test output load 25 ? 5pf dq v ddq 5pf v ddq 50 ? 50 ? v ddq ac characteristics parameter symbol -30 -25 unit note min max min max clock cycle time t khkh 3.3 - 4.0 - ns clock high pulse width t khkl 1.3 - 1.6 - ns clock low pulse width t klkh 1.3 - 1.6 - ns clock high to output valid t khqv -1.6-2.0ns clock high to output hold t khqx 0.5 - 0.5 - ns address setup time t avkh 0.3 - 0.3 - ns address hold time t khax 0.5 - 0.5 - ns write data setup time t dvkh 0.3 - 0.3 - ns write data hold time t khdx 0.5 - 0.5 - ns sw , sw [a:d] setup time t wvkh 0.3 - 0.3 - ns sw , sw [a:d] hold time t khwx 0.5 - 0.5 - ns ss setup time t svkh 0.3 - 0.3 - ns ss hold time t khsx 0.5 - 0.5 - ns clock high to output hi-z t khqz -1.7-2.0ns clock high to output low-z t khqx1 0.5 - 0.5 - ns g high to output high-z t ghqz -1.7-2.0ns g low to output low-z t glqx 0.5 - 0.5 - ns g low to output valid t glqv -1.7-2.0ns zz high to power down(sleep time) t zze - 15 - 15 ns zz low to recovery(wake-up time) t zzr - 20 - 20 ns
rev 1.3 k7p321888m 1mx36 & 2mx18 sram K7P323688M dec. 2005 - 9 - timing waveforms of normal active cycles (ss controlled, g =low) 1234 5678 k san ss sw sw x dqn note 1. d 3 is the input data written in memory location a 3 . 2. q 4 is the output data read from the write data buffer(not from the cell array), as a result of address a 4 being a match from the last write cycle address. a 1 a 2 a 3 a 4 a 5 a 4 a 6 a 7 q 1 d 3 d 4 q 5 q 4 timing waveforms of normal active cycles (g controlled, ss =low) 1234 5678 k san g sw sw x dqn note 1. d 3 is the input data written in memory location a 3 . 2. q 4 is the output data read from the write data buffer(not from the cell array), as a result of address a4 being a match from the last write cycle address. a 1 a 2 a 3 a 4 a 5 a 4 a 6 a 7 q 2 q 1 d 3 d 4 q 5 q 4 q 2 t khkh t khax t avkh t khkl t klkh t khsx t svkh t wvkh t khwx t wvkh t khwx t khqx1 t khqx t wvkh t khwx t khqv t khdx t khqz t dvkh t khdx t khkh t ghqz t glqx t glqv
rev 1.3 k7p321888m 1mx36 & 2mx18 sram K7P323688M dec. 2005 - 10 timing waveforms of standby cycles 12345678 k san ss sw sw x dqn zz a 2 a 1 a 2 a 3 q 1 q 2 q 1 a 1 t khkh t zze t zzr t khqv t khqv
rev 1.3 k7p321888m 1mx36 & 2mx18 sram K7P323688M dec. 2005 - 11 jtag instruction coding note : 1. places dqs in hi-z in order to sample all input data regardless of other sram inputs. 2. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 3. bypass register is initiated to v ss when bypass instruction is invoked. the bypass register also holds serially loaded tdi when exiting the shift dr states. 4. sample instruction does not places dqs in hi-z. 5. private is reserved for the exclusive use of samsung. this instruction should not be used. ir2 ir1 ir0 instruction tdo output notes 0 0 0 sample-z boundary scan register 1 0 0 1 idcode identification register 2 0 1 0 sample-z boundary scan register 1 0 1 1 bypass bypass register 3 1 0 0 sample boundary scan register 4 101 private 5 1 1 0 bypass bypass register 3 1 1 1 bypass bypass register 3 ieee 1149.1 test access port and boundary scan-jtag tap controller state diagram jtag block diagram sram core bypass reg. identification reg. instruction reg. control signals tap controller tdo m 2 m 1 tdi tms tck test logic reset run test idle 0 11 1 1 0 0 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir 1 1 1 1 1 the sram provides a limited set of ieee standard 1149.1 jtag fu nctions. this is to test the connectivity during manufacturing between sram, printed circuit board and other components. internal data is not driven out of sram under jtag control. in confor m- ance with ieee 1149.1, the sram contains a tap controller, instru ction register, bypass register and id register. the tap contr ol- ler has a standard 16-state machine that resets internally upon pow er-up, therefore, trst signal is not required. it is possibl e to use this device without utilizing the tap. to disable the tap contro ller without interfacing with normal operation of the sram, tck must be tied to v ss to preclude mid level input. tms and tdi are designed so an undriven input will produce a response identical to the application of a logic 1, and therefore can be left unconnected. but they may also be tied to v dd through a resistor. tdo should be left unconnected.
rev 1.3 k7p321888m 1mx36 & 2mx18 sram K7P323688M dec. 2005 - 12 id register definition part revision number (31:28) part configuration (27:18) vendor definition (17:12) samsung jedec code (11: 1) start bit(0) 1mx36 0000 01000 00100 xxxxxx 00001001110 1 2mx18 0000 01001 00011 xxxxxx 00001001110 1 boundary scan exit order(x36) 36 3b sa sa 5b 35 37 2b sa sa 6b 34 38 3a sa sa 5a 33 39 3c sa sa 5c 32 40 2c sa sa 6c 31 41 2a sa sa 6a 30 42 2d dqc 9 dqb 9 6d 29 43 1d dqc 8 dqb 8 7d 28 44 2e dqc 7 dqb 7 6e 27 45 1e dqc 6 dqb 6 7e 26 46 2f dqc 5 dqb 5 6f 25 47 2g dqc 4 dqb 4 6g 24 48 1g dqc 3 dqb 3 7g 23 49 2h dqc 2 dqb 2 6h 22 50 1h dqc 1 dqb 1 7h 21 51 3g sw c sw b5g 20 52 4d zq g 4f 19 53 4e ss k4k18 54 4b sa k 4l 17 55 4h nc* sw a5l 16 56 4m sw dqa 1 7k 15 57 3l sw d dqa 2 6k 14 58 1k dqd 1 dqa 3 7l 13 59 2k dqd 2 dqa 4 6l 12 60 1l dqd 3 dqa 5 6m 11 61 2l dqd 4 dqa 6 7n 10 62 2m dqd 5 dqa 7 6n 9 63 1n dqd 6 dqa 8 7p 8 64 2n dqd 7 dqa 9 6p 7 65 1p dqd 8 zz 7t 6 66 2p dqd 9 sa 5t 5 67 3t sa sa 6r 4 68 2r sa sa 4t 3 69 4n sa sa 4p 2 70 3r m 1 m 2 5r 1 boundary scan exit order(x18) 26 3b sa sa 5b 25 27 2b sa sa 6b 24 28 3a sa sa 5a 23 29 3c sa sa 5c 22 30 2c sa sa 6c 21 31 2a sa sa 6a 20 dqa 9 6d 19 32 1d dqb 1 33 2e dqb 2 dqa 8 7e 18 dqa 7 6f 17 34 2g dqb 3 dqa 6 7g 16 dqa 5 6h 15 35 1h dqb 4 36 3g sw b 37 4d zq g 4f 14 38 4e ss k4k13 39 4b sa k 4l 12 40 4h nc* sw a5l 11 41 4m sw dqa 4 7k 10 42 2k dqb 5 dqa 3 6l 9 43 1l dqb 6 44 2m dqb 7 dqa 2 6n 8 45 1n dqb 8 dqa 1 7p 7 zz 7t 6 46 2p dqb 9 sa 5t 5 47 3t sa sa 6r 4 48 2r sa 49 4n sa sa 4p 3 50 2t sa sa 6t 2 51 3r m 1 m 2 5r 1 scan register definition part instruction register bypass register id register boundary scan 1mx36 3 bits 1 bits 32 bits 70 bits 2mx18 3 bits 1 bits 32 bits 51 bits note :1. pin 4h is no connection pin to in ternal chip and the scanned data is "0". 1 1
rev 1.3 k7p321888m 1mx36 & 2mx18 sram K7P323688M dec. 2005 - 13 jtag dc operating conditions note : 1. the input level of sram pin is to follow the sram dc specification . parameter symbol min typ max unit note power supply voltage v dd 1.7 1.8 1.9 v input high level v ih 0.65 v dd -v dd +0.3 v input low level v il -0.3 - 0.35 v dd v output high voltage(i oh =-2ma) v oh v dd - 0.45 - v dd v output low voltage(i ol =2ma) v ol v ss -0.45v jtag timing diagram jtag ac characteristics parameter symbol min max unit note tck cycle time t chch 50 - ns tck high pulse width t chcl 20 - ns tck low pulse width t clch 20 - ns tms input setup time t mvch 5-ns tms input hold time t chmx 5-ns tdi input setup time t dvch 5-ns tdi input hold time t chdx 5-ns sram input setup time t svch 5-ns sram input hold time t chsx 5-ns clock low to output valid t clqv 010ns jtag ac test conditions note : 1. see sram ac test output load on page 7. parameter symbol min unit note input high/low level v ih /v il 1.8/0.0 v input rise/fall time tr/tf 1.0/1.0 ns input and output timing reference level 0.9 v 1 tck tms tdi pi t chch t mvch t chmx t chcl t clch t dvch t chdx t clqv tdo (sram) t svch t chsx
rev 1.3 k7p321888m 1mx36 & 2mx18 sram K7P323688M dec. 2005 - 14 119 bga package thermal characteristics note : 1. junction temperature can be calculated by : t j = t a + p d x theta_ja. parameter symbol thermal resistance unit note junction to ambient(at still air) theta_ja 20.0 c/w 1.5w heating junction to case theta_jc 4.3 c/w junction to board theta_jb 5.4 c/w 1.5w heating 119 bga package dimensions 119x 0.750 0.15 1.27 x 6 = 7.62 12.50 0.10 0.60 0.10 4x c1.00 4x c0.70 14.00 0.10 22.00 0.10 20.50 0.10 note : 1.all dimensions are in millimeters. 2. cavity surface : mat finish (rz 10~15um) pin surface : polish (rz 2um max) 3. solder ball to pcb offset : 0.10 max. 4. pcb to cavity offset : 0.10 max. 5. pkg warpage : 0.05 max # a1 index mark 2.00 2.00 1.00 dp 0.10 0.05 2.00 2.00 2.00 dp 0.10 0.05 0.15 max 0.30 max 1.27 x 16 = 20.32 1.27 1.27 a b c d e f g h j k l m n p r t u 2 5 5 0.56 0.04 0.90 0.05 1.50 0.10 2.21 max 1 2 3 4 5 6 7

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